1. Field of the Invention
The present invention relates to an output buffer circuit for avoiding voltage overshoot, and more particularly, to an output buffer circuit that prevents leakage currents from changing a systematic offset voltage by timely closing a clamping circuit.
2. Description of the Prior Art
An output stage of a present display driver adopts an operational amplifier circuit to rapidly charge and discharge a load end, such that driving capability of the display driver is enhanced. However, if inner currents of the operational amplifier cannot be recovered immediately, the rapid charging or discharging of the load end would a voltage overshoot. In general, a clamping circuit is added between an output terminal of the operational amplifier and an input terminal of the output stage thereof to avoid the voltage overshoot. However, under a situation that the operational amplifier has full swing output, the clamping circuit may not be completely closed, resulting in certain leakage currents (in approximate nA degree). For low power application, such leakage currents may change a systematic offset voltage of the display driver.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of an operational amplifier 10 according to the prior art. The operational amplifier 10 is a two stage amplifier, and includes an input stage 11, an output bias circuit 12, an output stage 13 and a clamping circuit 14. The input stage 11 is a differential input stage having a rail-to-rail input range, and includes a positive input terminal AVP and a negative input terminal AVN. The input stage 11 includes input transistors N1, N2, P1 and P2 coupled to the input terminals AVP and AVN and bias transistors N3 and P3 coupled to the bias terminals VBN1 and VBP1, respectively. The input stage 11 generates a current signal IAB according to an input voltage received by the positive input terminal AVP. The output bias circuit 12 is coupled to the input stage 11, for generating a dynamic bias VAB between nodes AA and AB (i.e. a voltage difference between the node AA and the node AB) according to the current signal IAB. The output stage 13 is a class AB output stage composed of transistors P9 and N9, and includes an input output terminal AVF reversely coupled to the negative input terminal AVN of the input stage 11. The output stage 13 provides a driving current to the output terminal AVF according to the dynamic bias VAB, so as to generate an output voltage. The clamping circuit 14 consists of transistors POS1, POS2, NOS1, and NOS2, for maintaining the output voltage of the operational amplifier 10 within a predefined range, so as to avoid the voltage overshoot.
When the operational amplifier 10 charges the load, such as receiving a high level input voltage, a voltage of the positive input terminal AVP increases, such that the current signal IAB flowing through the output bias circuit 12 decreases, and results in decrease of voltages of the nodes AA and AB. Under such circumstances, the output stage 13 increases the driving current for the output terminal AVF to enhance the output voltage of the operational amplifier, as shown by solid lines in FIG. 1. On the contrary, when the operational amplifier 10 discharges the load, such as receiving a low level input voltage, the voltage of the positive input terminal AVP decreases, such that the current signal IAB flowing through the output bias circuit 12 increases, and results in increase of the voltages of the nodes AA and AB. Under such circumstances, the output stage 13 reduces the driving current for the output terminal AVF to decrease the output voltage of the operational amplifier, as shown by dot lines in FIG. 1.
Under normal conditions, a level of the output voltage makes overdrive voltages of the transistors POS2 or NOS2 smaller than threshold voltages thereof, i.e. (AVF-VBPOS)<Vthp or (VBNOS-AVF)<Vthn, and results in the transistors POS2 or NOS2 being closed. Hence, the clamping circuit 14 has no effects on the charging and discharging operations of the operational amplifier. Whereas, when the level of the output voltage exceeds a predefined range, the overdrive voltages of the transistors POS2 or NOS2 are larger than the threshold voltages thereof, i.e. (AVF-VBPOS)>Vthp or (VBNOS-AVF)>Vthn, which results in the transistors POS2 or NOS2 being on. In this case, currents flowing from the output terminal AVF into the nodes AA or AB help the voltages of the nodes AA or AB to return to a normal level, so as to alleviate the voltage overshoot.
However, incases that the operational amplifier has full swing output, the transistors POS2 or NOS2 may not be completely closed, resulting in a certain leakage currents. Take the discharging operation as an example, the output voltage of the operational amplifier may be as low as 0.1 volt, thereby the transistors NOS1 and NOS2 cannot be completely closed, and results in a certain currents flowing through the transistors NOS1 and NOS2 (from the output terminal AVF into the node AB). For the low power application, currents of each path in the operational amplifier become lower and lower, thereby it becomes obvious that variations of currents flowing through the transistors P11 and N11 and a variation of the overdrive voltage caused by the leakage currents, so as to influence a bias status and a static current of the output stage 13. With a change to the static current of the output stage 13, a transconductance of the output stage 13 and a gain of the operational amplifier would also vary. The gain of the operational amplifier directly influences a systematic offset voltage of the operational amplifier.
In brief, for the low power application, the current of each path of the operational amplifier becomes lower with time. In the full swing output case, the clamping circuit cannot be completely closed, resulting in a more obvious change to the static current of the output bias circuit. Accordingly, the gain of the whole operational amplifier changes, so as to influence the systematic offset voltage of the operational amplifier.